PXI Architecture - PCI and PCI Express Communication
PCI and PCI Express Communication
The PCI bus gained adoption as a mainstream computer bus in the mid-1990s. The most common implementation of the PCI bus operates at 33 MHz and 32 bits with a peak theoretical bandwidth of 132 MB/s and is the implementation employed in the majority of PXI systems. It uses a shared bus topology, where bus bandwidth is divided among multiple devices, to enable communication among the different devices on the bus. Over time, some devices have become more bandwidth-hungry. As a result, PCI Express was created to overcome the limitations associated with a shared bus architecture.
The most notable PCI Express advancement compared to PCI is its point-to-point bus topology. The shared bus used for PCI is replaced with a shared switch, which gives each device its own direct access to the bus. Unlike PCI, which divides bandwidth between all devices on the bus, PCI Express provides each device with its own dedicated data pipeline. Data is sent serially in packets through pairs of transmit-and-receive signals called lanes, which offers 250 MB/s bandwidth per direction, per lane for PCI Express 1.0. Multiple lanes can be grouped together into x1 (“by one”), x2, x4, x8, x12, and x16 lane widths to increase bandwidth to the slot – achieving up to 4 GB/s total throughput. Since the introduction of PCI Express, the standard has evolved to allow faster data rates while maintaining backward compatibility. For instance, PCI Express 2.0 doubles the per-lane bandwidth from 250 to 500 MB/s per direction.