PXI Architecture - Timing and Synchronization
Timing and Synchronization
One of the key advantages of a PXI system is the integrated timing and synchronization resources. A standard PXI chassis incorporates a dedicated 10 MHz system reference clock, a PXI trigger bus, a star trigger bus, and a slot-to-slot local bus to address the need for advanced timing and synchronization. These timing signals are dedicated signals in addition to the communication architecture. The 10 MHz clock within the chassis can be exported or replaced with a higher-stability reference. This allows the sharing of the 10 MHz reference clock between multiple chassis and other instruments that can accept a 10 MHz reference. By sharing this 10 MHz reference, higher-sample-rate clocks can be synchronized to the stable reference, providing timing coherence and improving the sample alignment between multiple instruments. In addition to the reference clock, PXI provides eight TTL lines as a trigger bus. This allows any module in the system to send or receive a trigger based on an instrument or externally generated event. Finally, the local bus provides a means to establish dedicated communication between adjacent modules.
Building on PXI capabilities, PXI Express provides the additional timing and synchronization features of a 100 MHz differential system clock, differential signaling, and differential star triggers. By using differential clocking and synchronization, PXI Express systems benefit from increased noise immunity for instrumentation clocks and the ability to transmit at higher-frequency rates. PXI Express chassis provide these more advanced timing and synchronization capabilities in addition to all of the standard PXI timing and synchronization signaling.